In this specification, the term integrated circuit is used to describe a chip or MCM (multi-chip module), embedded with DFT (design-for-test) techniques.
The scan-based DFT technique is the most widely used method for producing high quality integrated circuits. The scan-based DFT technique requires that all storage elements (sequential logic gates) existing in an integrated circuit, such as D flip-flops, be replaced with their scan-equivalent storage elements, such as Scan D flip-flops, otherwise known as scan cells (SCs). These scan cells are then connected to form one or more scan chains each controlled by one or more scan enable (SE) signals and scan clocks (SCKs) each belonging to a separate clock or frequency domain, see FIG. 1.
Testing a scan-based integrated circuit proceeds in a sequence of shift and capture operations, which are repeated for a number of test patterns. In order to distinguish between shift and capture operations, a scan enable (SE) signal local to all scan cells in a clock domain is used to select either the shift path or the functional path as the path to provide a new value to update a scan cell. In the shift operation, the shift path is selected in order to shift desired test stimuli into scan cells belonging to all the different scan chains and at the same time shift captured test responses out for comparison with expected values. In the capture operation, the functional path is selected in order to update the scan cells with the test response from the combinational part of the scan-based integrated circuit.
Test stimuli are shifted into scan chains through input pads and test responses are shifted out through output pads. These I/O pads are usually designed for use in functional mode, and can usually operate at very high frequencies, ranging from a few hundred MHz to a few GHz. However, scan chains, which are only used in test mode, usually only operate at a much lower frequency, ranging from 10 MHz to 100 MHz. Designing scan chains that operate at the same high frequency as I/O pads places a big burden on the design team, and increases risks for introducing too much peak power consumption during test. As a result, a big gap usually exists between the frequency at which I/O pads tied to scan chains operate in test mode, and the frequency at which these I/O pads operate in functional mode. Operating the scan chains and I/O pads at a lower frequency in test mode has the disadvantage of increasing test time and test cost. Furthermore, this prevents us from being able to test the I/O pads at-speed during test, which can reduce test quality or increase test cost, by requiring a separate at-speed test for these I/O pads.
Prior art solution #1, see FIG. 2, uses pairs of decompressors and compressors to reduce test time, test cost, and test data volume of a scan-based integrated circuit during scan test. The U.S. Pat. No. 6,327,687, co-authored by Rajski et al., described a general design of the decompressor and compressor. The U.S. Patent Application 2003/0154433, co-authored by Wang et al., described another general design of the decompressor and compressor, called broadcaster and compactor, respectively. All decompressors and compressors are, in general, operated at the same frequency as the scan-based integrated circuit. Although this solution results in a reduction in test time, test cost, and test data volume, it needs to operate all high-speed I/O pads at a low frequency in test mode. This means that a separate set of test patterns are required to test these I/O pads.
Prior art solution #2, see FIG. 3A and FIG. 3B, uses pairs of time-division demultiplexors (TDDMs) and time-division multiplexors (TDMs) to allow each high-speed I/O pad to operate at a high frequency or at its respective clock rate (at-speed), while operating the internal scan chains at a low frequency. The time-division demultiplexors (TDDMs) are used to demultiplex high-frequency scan data applied to each scan input I/O pad into low-frequency scan data applied to multiple scan-chains. Similarly, the time-division multiplexors (TDMs) are used to multiplex low-frequency scan data from multiple scan chains into high-frequency scan data coming out of each scan output I/O pad. This way, the I/O pads and scan chains can operate at different frequencies during test. Although this solution does result in a reduction in test time and test cost as opposed to operating both I/O pads and scan chains at a low frequency, it does not result in a reduction in the test data volume.
Therefore, there is a need for an improved method and apparatus for further reducing test time, test cost, and test data volume, while at the same time allowing all high-speed I/O pads to operate at high frequencies or at their respective clock rates. The improved method and apparatus shall also allow for reduced pin-count test to ease production test, prototype debug, fault diagnosis, and yield improvement.